Samsung Electronics, one of the leading players in the semiconductor market, has announced a new chip packaging technology called the I-Cube4 (Interposer-Cube4). The I-Cube4 comes as a successor to the I-Cube2 which made its debut in 2018. The I-Cube 4 uses the brand’s “next-generation 2.5D technology” and is aimed at “high-performance applications”. Samsung says that the I-Cube4 can offer faster performance and better power efficiency, among other benefits. The new packing technology, according to the brand, is available immediately. Let us have a deeper look at the I-Cube4 chip packaging technology.
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Samsung I-Cube4 packaging process detailed
According to Samsung, I-Cube4 is a heterogeneous integration technology that allows horizontal placement of one logic die (CPU, GPU, etc) and four High Bandwidth Memory (HBM) dies on top of a silicon interposer, which makes it possible to operate multiple dies on a single chip in one package. With this arrangement, the I-Cube4 is claimed to offer faster communication between logic and memory, and also provide better power efficiency. The brand says that I-Cube4 is ideal for high-performance computing (HPC) applications such as AI, 5G, cloud, and large data centers.
The press release notes that the silicon interposer is thinner than paper and, therefore, is subject to warping and bending, which negatively impacts the product quality. However, Samsung is said to have studied how to control interposer warpage and thermal expansion by changing material and thickness.
Samsung says that it has developed a “mold-free” structure for the I-Cube4 which efficiently removes heat. Plus, Samsung will conduct a pre-screening test that can filter out defective units which will lead to increased production. All these optimisations, according to the brand, led to the commercialisation of the I-Cube4.
Samsung is also developing I-Cube6
Samsung also took the opportunity to announce that it is working on the I-Cube6, a successor to the now-announced I-Cube4. The I-Cube6, according to the company, will have a “combination of advanced process nodes, high-speed interface IPs and advanced 2.5/3D packaging technologies, which will help customers design their products in the most effective way.”
